Response to chan

ABSTRACT

REGISTER AVAILABLE WHEN IT ARRIVES AT THE STORAGE CONTROL UNIT.   A LARGE SCALE DATA PROCESSING SYSTEM HAVING A HIGH SPEED LOW CAPACITY BUFFER STORE FOR BUFFERING DATA FETCH AND DATA STORE REQUESTS TO A LOW SPEED HIGH CAPACITY INTERLEAVED MAIN STORAGE. REQUESTS FOR STORAGE MAY COME FROM A PLURALITY OF CHANNELS WHICH COMMUNICATE WITH A STORAGE CONTROL UNIT (SCU) OVER SHARED ADDRESS AND DATA BUSES. MULTIPLE CHANNEL REQUESTS ARE SEQUENCED OVER THIS SHARED BUS. THE STORAGE CONTROL UNIT CONTROLS THIS SEQUENCING BY MEANS OF PRIORITY CIRCUITS AND UPON GRANTING PRIORITY TO ONE OF THE CHANNELS, PROVIDES FOR MEMORY SELECTION. IN THE CASE OF MULTIPLE SIMULTANEOUS CHANNEL REQUESTS, THE STORAGE CONTROL UNIT UNCONDITIONALLY ACCEPTS A REQUEST EVERY MEMORY CYCLE. UPON ARRIVAL AT THE STORAGE CONTROL UNIT, THE ADDRESS AND DATA CORRESPONDING TO THE REQUEST ARE HELD IN REGISTERS PENDING THE AVAILABILITY OF THE REQUESTED STORAGE THEREBY FREEING THE CHANNEL BUS FOR ACCEPTANCE OF ANOTHER REQUEST. THE MAXIMUM DELAY THAT THE REGISTERED REQUEST CAN ENCOUNTER IS ONE MEMORY CYCLE, THEREFORE, THE NEXT ACCEPTED REQUEST WILL FIND THE

710-74 Y5506 on SR ssosv OR r 915,002

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 0.6. 687. The abstracts ot Detenlivelublication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each obstruct indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally died. The dies 0! these applications are available to the public for inspection and reproduction may be purchased for Q0 cents a sheet.

Defensive Publication applications have not been examined as to the merits ot alleged invention. The Patent Omce makes no assertion u to the novelty ot the disclosed subject matter.

PUBLISHED OCTOBER 9, 1973 T915,002 CHANNEL-MEMORY BUS CONTROL Gerry D. Granito, Poughireepsle, N.Y., asslgnor to Inter- 1nIatlYonal Business Machines Corporation, Armonk,

Continuation-impart of application Ser. No. 46,081, June 15, 1970. This application Oct. 13, 1972, Ser.

Int. Cl. Gllc 25/00 U.S. Cl. Mil-172.5 8 Sheets Drawing. 2! Pages Specification MAIN SVOIAGE mm HMIIL lliEi FIR JOKE A large scale data processing system having a high speed low capacity buifcr store for buffering data fetch and data store requests to a low speed high capacity in tcrleavcd main storage. Requests for storage may come from a plurality of channels which communicate with a storage control unit (SCU) over shared address and data buses. Multiple channel requests are sequenced over this shared bus. The storage control unit controls this sequencing by means of priority circuits and upon granting priority to one of the channels, provides for memory selection. In the case of multiple simultaneous channel requests, the storage control unit unconditionally accepts a request every memory cycle. Upon arrival at the storage control unit, the address and data corresponding to the request are held in registers pending the availability of the requested storage thereby freeing the channel bus for acceptance of another request. The maximum delay that the registered request can encounter is one memory cycle, therefore, the next accepted request will find the register available when it arrives at the storage control unit.

ssosv Oct. 9, 1973 Filed Oct. 13, 1972 FIG, 5 PRIORITY LOGIC B Sheets-Sheet '7 i a !CHAN N HI PRlORlTY I I T i m I I /CHAN 3 a1 PRIORITY I I 5 I a I I I I 155 I I CHAN 2 HI PRIORITY I I 8 *fl I 153 we I 1 I cm HI PRIORITY I I l HAN P I Y I 5 0R is R CCLE FIG.6

RESPONSE TO CHAN 2 RESPONSE TO CHAN 3 POTENTIAL DRUM OVER RUN DETECTOR LOGiC FOR 3RD CHAN a BLOCK CPE T0 CORE a woman RESET BLOCK COUNTER RESPONSE cm 10 a 

